1. Field of the Invention
The present invention relates to an image display device and a method of driving the same. For example, the present invention can be applied to an active matrix type image display device using organic Electro Luminescence (EL) elements. In the present invention, the electric charges originating from which a voltage developed across opposite terminals of a hold capacitor are discharged through a drive transistor, thereby correcting a dispersion of threshold voltages of the drive transistors. In this case, a gate-to-source voltage of the drive transistor is reduced for a time period for which the discharge of the electric charges corresponding to the voltage developed across the opposite terminals of the hold capacitor is temporarily stopped by utilizing running between wiring patterns formed on a substrate. Thus, in the present invention, it is made possible to reliably correct the dispersion of the threshold voltages of the drive transistors even when the discharge of the electric charges corresponding to the voltage developed across the opposite terminals of the hold capacitor is carried out for each of multiple time periods so as to correct the dispersion of the threshold voltages of the drive transistors by discharging the electric charges corresponding to the voltage developed across the opposite terminals of the hold capacitor through the drive transistor.
2. Description of the Related Art
Heretofore, in an active matrix type image display device using organic EL elements, a display portion is formed by disposing pixel circuits each composed of the organic EL element and a drive circuit for driving the organic EL element in a matrix. With this sort of image display device, a signal line driving circuit and a scanning line driving circuit which are disposed in a periphery of the display portion successively drive the pixel elements, thereby displaying a desired image on the display portion.
With regard to the image display device using the organic EL elements, Japanese Patent Laid-Open No. 2007-310311 (hereinafter referred to as Patent Document 1) discloses a method of configuring one pixel circuit by using two transistors. Therefore, according to the method disclosed in Patent Document 1, the configuration can be simplified.
In addition, Patent Document 1 also discloses a configuration with which a dispersion of threshold voltages of drive transistors for driving respective organic EL elements, and a dispersion of mobilities thereof are corrected. Therefore, according to the configuration disclosed in Patent Document 1, it is possible to prevent image quality from being deteriorated due to the dispersion of the threshold voltages of the drive transistors, and the dispersion of the mobilities thereof.
On the other hand, Japanese Patent Laid-Open No. 2007-133284 (hereinafter referred to as Patent Document 2) proposes a configuration with which processing for correcting the dispersion of the threshold voltages is executed for each of the multiple time periods.
Here, with the image display device using the organic EL elements, the organic EL elements are current-driven by using the drive transistors each composed of a Thin Film Transistor (TFT), respectively. Here, the TFT has a disadvantage that there is the large dispersion in the characteristics. In the image display device using the organic EL elements, the image quality is remarkably deteriorated owing to the dispersion, of the thresholds, as one of the dispersions of the characteristics of the drive transistors. It is noted that the deterioration of the image quality is perceived in the form of a streak, non-uniformity of a luminance, or the like.
More specifically, a drive current Ids caused to flow through an organic EL element by a driving operation of a drive transistor is expressed by Expression (1):Ids=(β/2)×(Vgs−Vth)2  (1)
where Vgs is a gate-to-source voltage of the drive transistor, and Vth is a threshold voltage of the drive transistor. In this case, a factor β in Expression (1) is given by Expression (2):β=μ×(W/L)×Cox  (2)
where μ is a mobility of a carrier in the drive transistor, W is a channel width of the drive transistor, L is a channel length of the drive transistor, and Cox is a capacitance of a gate insulating film, per unit area, of the drive transistor.
Therefore, in the image display device using the organic EL elements, when the threshold voltage Vth of the drive transistor disperses, the drive current Ids caused to flow through the organic EL element by the driving operation of the drive transistor disperses accordingly. As a result, an emission luminance disperses every pixel.
Here, Expression (1) is transformed into Expression (3):Vgs={Ids×(2/β)}1/2+Vth  (3)
Therefore, when the organic EL element is driven with a drive current Iref, the gate-to-source voltage Vref can be expressed by Expression (4):Vref={Iref×(2/β)}1/2+Vth  (4)
Therefore, when a pixel circuit is configured in such a way that the gate-to-source voltage Vgs of the drive transistor is set with a difference voltage Vdata obtained from the voltage Vref, Expression (5) can be obtained:Ids=(β/2)×[Vdata−{Iref×(2/β)}1/2]2  (5)
Therefore, in this case, in the image display device, it is possible to avoid an influence which the threshold voltage Vth is exerted on the drive current Ids. Also, it is possible to prevent the emission luminance from dispersing due to the dispersion of the threshold voltages Vth.
It is noted that when Iref=0, Expression (6) can be obtained:Ids=(β/2)×Vdata2  (6)
Therefore, in the image display device, even when Iref=0, it is possible to avoid an influence which the threshold voltage Vth is exerted on the drive current Ids. As a result, it is possible to prevent the image quality from being deteriorated. It is noted that when Iref=0, the configuration of the image display device can be simplified because there is no need for providing a current source for the drive current Iref.
With the configuration of the image display device disclosed in Patent Document 1, the dispersion of the threshold voltages of the drive transistors is corrected in accordance with the correction principle described above. Here, FIG. 12 is a block diagram showing an image display device to which the technique disclosed in Patent Document 1 is applied. In the image display device 1, a display portion 2 is formed on a transparent insulating substrate made of a glass or the like. Also, in the image display device 1, a signal line driving circuit 3 and a scanning line driving circuit 4 are provided in the periphery of the display portion 2.
Here, the display portion 2 is formed by disposing the pixel circuits 5 in a matrix. The signal line driving circuit 3 outputs drive signals Ssig for instruction for emission luminances to signal lines provided in the display portion 2. More specifically, after successively latching image data D1 inputted thereto in the order of the raster scanning, and distributing the image data D1 thus latched among the signal lines sig, the signal line driving circuit 3 executes processing for digital-to-analog converting the image data D1 thus distributed, thereby generating the drive signals Ssig. As a result, the image display device 1 sets gradations for the pixel circuits 5, for example, in the so-called line-sequential manner.
The scanning line driving circuit 4 outputs a write signal WS and a drive signal DS to scanning lines VSCAN1 and VSCAN2 provided in the display portion 2, respectively. Here, the write signal WS is a signal in accordance with which a write transistor provided in the pixel circuit 5 is controlled so as to be turned ON/OFF. In addition, the drive signal DS is a signal in accordance with which a drain voltage of a drive transistor provided in the pixel circuit 5 is controlled. The scanning line driving circuit 4 processes a timing signal outputted from a timing generator (not shown) in scanners 6A and 6B, thereby generating the write signal WS and the drive signal DS.
FIG. 13 is a circuit diagram, partly in block, showing a configuration of the pixel circuit 5 in detail. In the pixel circuit 5, a cathode terminal of an organic EL element 8 is connected to a predetermined fixed power source VSS1, and an anode terminal of the organic EL element 8 is connected to a source of a drive transistor Tr3. It is noted that the drive transistor Tr3 is an N-channel transistor, for example, composed of a TFT. Also, in the pixel circuit 5, a drain of the drive transistor Tr3 is connected to the scanning line VSCAN2 for power source supply. Thus, in the pixel circuit 5, the organic EL element 8 is current-driven by using the drive transistor Tr3 having a source follower circuit configuration.
In the pixel circuit 5, a hold capacitor Cs is connected between a gate and the source of the drive transistor Tr3. A voltage at a gate side end of the hold capacitor Cs is set at a voltage corresponding to the drive signal Ssig in accordance with the write signal WS.
As a result, in the pixel circuit 5, the organic EL element 8 is current-driven by the drive transistor Tr3 in accordance with the gate-to-source voltage Vgs corresponding to the drive signal Ssig. It is noted that in FIG. 13, a capacitance Coled is a floating capacitance of the organic EL element 8. In addition, in the following description, the Coled is sufficiently larger than that of the hold capacitor Cs, and a parasitic capacitance of a gate node of the drive transistor Tr3 is sufficiently smaller than the capacitance of the hold capacitor Cs.
That is to say, in the pixel circuit 5, the gate of the drive transistor Tr3 is connected to the signal line sig through a write transistor Tr1 which operates so as to be turned ON/OFF in accordance with the write signal WS. Here, the signal line driving circuit 3 switches one of the voltage Vsig for gradation setting, and a fixed voltage Vofs for threshold voltage correction to the other at a predetermined timing through switch circuits 9 and 10 which operate so as to be turned ON in accordance with predetermined control signals SELsig and SELofs, respectively, thereby outputting the drive signal Ssig.
Here, it is noted that the fixed voltage Vofs for threshold voltage correction is a fixed voltage used to correct the dispersion of the threshold voltages Vth of the drive transistors Tr3. In addition, the voltage Vsig for gradation setting is a voltage in accordance with which an emission luminance of corresponding one of the pixels is instructed, and is obtained by adding the fixed voltage Vofs for threshold voltage correction to a gradation voltage Vdata.
In addition, the gradation voltage Vdata is a voltage corresponding to the emission luminance of the pixel circuit 5 connected to the corresponding one of the signal lines sig. After successively latching the image data D1 inputted thereto in the order of the raster scanning, and distributing the image data D1 thus latched among the signal lines sig, a data receiver 6 composed of a semiconductor integrated circuit executes processing for digital-to-analog converting the image data D1 thus distributed, thereby generating the gradation voltage Vdata every signal line sig. It is noted that each of the switch circuits 9 and 10 is composed of a TFT, and is formed together with a wiring pattern composing the signal line sig, and the scanning lines VSCAN1 and VSCAN2 on the transparent insulating substrate having the pixel circuits 5 formed thereon.
In the pixel circuit 5, the write transistor Tr1 is set in an OFF state in accordance with the write signal WS for a time period for which the organic EL element 8 is caused to emit a light (hereinafter referred to as “an emission time period”) as indicated by “EMISSION” in a drive state (refer to FIG. 14G) in FIGS. 14A and 14G. In addition, in the pixel circuit 5, a power source voltage VDDV2 is supplied to the drive transistor Tr3 in accordance with the drive signal DS for a power source for the emission time period. As a result, in the pixel circuit 5, the organic EL element 8 is caused to emit a light with the drive current Ids corresponding to the gate-to-source voltage Vgs depending on a gate voltage Vg and a source voltage Vs (refer to FIGS. 14E and 14F) of the drive transistor Tr3 as a voltage developed across the opposite terminals of the hold capacitor Cs for the emission time period (refer to Expression (1)).
In the pixel circuit 5, the drive signal DS for a power source is caused to drop to the fixed voltage VSSV2 at a time point t0 at which the emission time period ends. Here, the fixed voltage VSSV2 is a voltage which is low enough to cause the drain of the drive transistor Tr3 to function as the source thereof, and which is lower than the cathode voltage VSS1 of the organic EL element 8. As a result, in the pixel circuit 5, the electric charges accumulated at the organic EL element 8 side end of the hold capacitor Cs are caused to flow out through the drive transistor Tr3 into the scanning line VSCAN2. As a result, in the pixel circuit 5, the source voltage Vs of the drive transistor Tr3 drops to the fixed voltage VSSV2, thereby stopping the light emission of the organic EL element 8.
In the pixel circuit 5, the switch circuit 10 on the fixed voltage Vofs side is set in an ON state at a predetermined time point t1 next to the time point t0. As a result, in the pixel circuit 5, the voltage of the signal line sig is set at the fixed voltage Vofs (refer to FIG. 14C). After that, in the pixel circuit 5, the write transistor Tr1 is switched from the OFF state over to the ON state in accordance with the write signal WS (refer to FIG. 14A). As a result, in the pixel circuit 5, the gate voltage Vg of the drive transistor Tr3 is set at the fixed voltage Vofs. Here, it is noted that the fixed voltage Vofs is a voltage with which no drive transistor Tr3 is turned ON right after the voltage developed across the opposite terminals of the hold capacitor Cs which will be described later is set at the threshold voltage Vth. Specifically, the fixed voltage Vofs needs to fulfill Expression (7):Vofs<VSS1+Vtholed+Vth  (7)
where Vtholed is a threshold voltage of the organic EL element 8.
As a result, in the pixel circuit 5, the gate-to-source voltage Vgs of the drive transistor Tr3 is set at a voltage (Vofs−VSSV2). Here, in the pixel circuit 5, the voltage (Vofs−VSSV2) is set so as to become higher than the threshold voltage Vth of the drive transistor Tr3 in accordance with the setting of the fixed voltages Vofs and VSSV2.
After that, in the pixel circuit 5, the drain voltage of the drive transistor Tr3 is caused to rise to the power source voltage VDDV2 at a time point t2 (refer to FIGS. 14A to 14C). As a result, in the pixel circuit 5, a charge current is caused to flow from the power source VDDV2 into the organic EL element 8 side end of the hold capacitor Cs through the drive transistor Tr3. As a result, in the pixel circuit 5, a voltage Vs at the organic EL element 8 side end of the hold capacitor Cs gradually rises. In this case, it is noted that since in the pixel circuit 5, the fixed voltage Vofs is set so as to fulfill Expression (7), the current caused to flow into the organic EL element 8 through the drive transistor Tr3 is used only to charge both the capacitance Coled of the organic EL element 8, and the hold capacitor Cs. As a result, in the pixel circuit 5, the organic EL element 8 emits no light, and thus only the source voltage Vs of the drive transistor Tr3 simply rises.
Here, when in the pixel circuit 5, a potential difference developed across the opposite terminals of the hold capacitor Cs becomes equal to the threshold voltage Vth of the drive transistor Tr3, the flowing of the charge current into the organic EL element 8 through the drive transistor Tr3 is stopped. Therefore, in this case, when the potential difference developed across the opposite terminals of the hold capacitor Cs becomes equal to the threshold voltage Vth of the drive transistor Tr3, the rising of the source voltage Vs of the drive transistor Tr3 is stopped. As a result, in the pixel circuit 5, the electric charges corresponding to the voltage developed across the opposite terminals of the hold capacitor Cs are discharged through the drive transistor Tr3, and thus the voltage developed across the opposite terminals of the hold capacitor Cs is set at the threshold voltage Vth of the drive transistor Tr3.
When in the pixel circuit 5, at a time point t3 is reached after a lapse of time enough to set the voltage developed across the opposite terminals of the hold capacitor Cs at the threshold voltage Vth of the drive transistor Tr3, the write transistor Tr1 is switched from the ON state to the OFF state in accordance with the write signal WS (refer to FIG. 14A). As a result, in the pixel circuit 5, the voltage developed across the opposite terminals of the hold capacitor Cs is reduced for a time period from the time point t2 to the time point t3 to be set at the threshold voltage Vth of the drive transistor Tr3.
In the pixel circuit 5, after the switch circuit 10 on the side of the fixed voltage Vofs is subsequently switched from the ON state to the OFF state, the switch 9 on the side of the voltage Vsig for gradation setting is set in the ON state (refer to FIGS. 14C and 14D). As a result, in the pixel circuit 5, the voltage of the signal line sig is set at the voltage Vsig for gradation setting. In addition, in the pixel circuit 5, the write transistor Tr1 is set in the ON state at a time point t4 following the time point t3. As a result, in the pixel circuit 5, the gate voltage Vg of the drive transistor Tr3 gradually rises from the state in which the potential difference developed across the opposite terminals of the hold capacitor Cs is set at the threshold voltage Vth of the drive transistor Tr3 to be set at the voltage Vsig for gradation setting. As a result, in the pixel circuit 5, as previously stated with respect to Expression (7), the gate-to-source voltage Vgs of the drive transistor Tr3 is set at the difference voltage Vdata obtained based on the voltage Vref. As a result, in the pixel circuit 5, it is possible to prevent the drive current Ids from dispersing due to the dispersion of the threshold voltages Vth of the drive transistors Tr3. Thus, it is possible to prevent the dispersion of the emission luminances.
In the pixel circuit 5, while the drain voltage of the drive transistor Tr3 is held at the power source voltage VDDV2, for a given time period Tμ, the gate of the drive transistor Tr3 is connected to the signal line sig, so that the gate voltage Vg of the drive transistor Tr3 is set at the voltage Vsig for gradation setting. As a result, in the pixel circuit 5, the dispersion of the mobilities μ of the drive transistors Tr3, together with this operation, are corrected.
Here, a write time constant necessary for rising of the gate voltage Vg of the drive transistor Tr3 made through the write transistor Tr1 is set so as to be shorter than a time constant necessary for rising of the source voltage Vs by the driving operation of the drive transistor Tr3. In the following description, the write time constant necessary for rising of the gate voltage Vg of the drive transistor Tr3 is assumed to be negligibly smaller than the time constant necessary for rising of the source voltage Vs.
In this case, when the write transistor Tr1 is turned ON, the gate voltage Vg of the drive transistor Tr3 rapidly rises to the voltage Vsig (Vofs+Vdata) for gradation setting. In the phase of the rising of the gate voltage Vg, when the capacitance Coled of the organic EL element 8 is sufficiently larger than that of the hold capacitor Cs, no source voltage Vs of the drive transistor Tr3 changes.
However, when the gate-to-source voltage Vgs of the drive transistor Tr3 increases to exceed the threshold voltage Vth, the drive current Ids is caused to flow from the power source VDDV2 through the drive transistor Tr3, so that the source voltage Vs of the drive transistor Tr3 gradually rises. As a result, in the pixel circuit 5, the electric charges corresponding to the voltage developed across the hold capacitor Cs are discharged through the drive transistor Tr3, so that a rising speed of the gate-to-source voltage Vgs decreases.
The discharging speed of the electric charges corresponding to the voltage developed across the hold capacitor Cs changes depending on a capability of the drive transistor Tr3. More specifically, the discharging speed increases as the mobility μ of the drive transistor Tr3 becomes larger. It is noted that the drive current Ids of the drive transistor Tr3 on which the discharging speed depends can be expressed by Expression (8):Ids=(β/2)×{(1/Vdata)+(β/2)×(Tμ/C)}−2  (8)
where C is given by (Cs+Coled).
As a result, in the pixel circuit 5, the setting is made in such a way that the voltage developed across the opposite terminals of the hold capacitor Cs is further reduced in the drive transistor Tr3 having the larger mobility μ. Thus, the dispersion of the emission luminances caused by the dispersion of the mobilities is corrected. In the pixel circuit 5, after a lapse of the time period Tμ, the write signal WS is caused to drop, and the switch circuit 9 on the side of the voltage Vsig for gradation setting is switched from the ON state to the OFF state. As a result, in the pixel circuit 5, the emission time period starts, and the organic EL element 8 is caused to emit a light by the drive current corresponding to the voltage developed across the opposite terminals of the hold capacitor Cs. It is noted that at this time, the power source voltage VDDV2 needs to be set so that the drive transistor Tr3 operates in a saturated region. More specifically, the power source voltage VDDV2 needs to be set so as to fulfill a relationship of {VDDV2>VEL+(Vgs−Vth)}.